DESIGN-MANAGEMENT TOOL Designsync 3.0 is an Internet-based design management and collaboration tool, which increases operational speed and adds new branch and merge functionality for parallel development. Branching and merging are the primary requirements, which enable parallel development. Branching allows a new line of development to be separated off of a base line. The work on a branch can be merged into another branch or discarded. Designsync 3.0 is available now and pricing starts at $3,000 per user. Designsync runs on Solaris, HP-UX, Windows 9x, and Windows NT. Contact Synchronicity, Inc. Marlboro, MA www.synchronicity.com

FUNCTIONAL VERIFICATION TOOL Surelint version 2.0 offers faster, more accurate race detection and finite state machine analysis capabilities and a new category of built-in Reuse Methodology Manual checks. The tool also includes user-defined checks, which enables users to add their own checks and messages to Surelint's library of built-in checks. The tool provides a library of Verilog Programming Interface (VPI) routines and property extensions that simplify the coding of custom checks in either C/C++ or Perl. Users have the ability to add any type of check, including naming conventions, Verilog language restrictions, or assignment style checks. The user-defined checks, and their associated messages, can be viewed and processed in the same manner as the tool's built-in checks and messages. Surelint 2.0 is available now on the Linux operating system, Solaris and HP workstations running HP-UX. The price of the tool is $15,000 for a floating LAN license. Contact Verisity Rosh Ha'ain, Israel www.verisity.com

PROGRAMMABLE SOC C8051F011 is a field-programmable, mixed-signal system-on-a-chip (SOC) targeted at system management applications. C8051F011 was designed to offer a programmable solution to the problem of controlling/monitoring temperature, supply voltage, fans, and intrusion within servers, storage area networks, telecom switching equipment, and embedded systems. The programmable SOC combines a 10-bit precision analog-to-digital converter (ADC), two 12-bit digital-to-analog converters (DACs) and dual voltage comparators, a 20 MIPS peak 8051-compatible CPU, and 32K bytes of in-system programmable FLASH memory. Digital peripherals include a UART, an SMBus and a SPI serial interface port, four 16-bit timers, and a five-channel programmable counter array (PCA). The C8051F011 is available in a 48-pin TQFP and sells for $10.75 in 1,000 piece quantities, and the C8051F010DK development kit sells for $99.00. Contact Cygnal Integrated Products, Inc. Austin, TX www.cygnal.com

TESTBENCH DESIGN AND ANALYSIS TOOL Bestbench 4.0 now adds the generation of Verilog-based testbenches to its VHDL-based testbench design environment. Bestbench offers a dual HDL design and analysis tool that automates the creation, debug, and reuse of testbenches. The tool, with its Evaluator technology, allows testbenches to be designed and debugged independently from the UUT. With the tool, HDL designers develop a transaction-based testbench as a data flow of stimuli and expected results using HDL code, waveforms, text I/O files, bus functional models, or C models. From the specified sequence of transactions, the self-checking testbench HDL code is generated. Bestbench 4.0 is licensed in 3 ways: Bestbench/VHDL, Bestbench/Verilog, and Bestbench/Dual. Bestbench runs on both UNIX workstations (Sun and HP) and PC-NT platforms. The software can be downloaded and evaluation licenses requested at no charge. Contact Diagonal Systems Zurich, Switzerland www.diagonal.com